Device ESD protection capability evaluation quantifies the ability of semiconductors and electronic components to survive electrostatic discharge events that occur during manufacturing, handling, assembly, and end-use operation. By applying standardized stress models such as the Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM), accredited third-party laboratories determine component robustness levels, support qualification to standards including ANSI/ESDA/JEDEC JS-001, ANSI/ESDA/JEDEC JS-002, IEC 61000-4-2, and AEC-Q100, and help manufacturers reduce field failure risk. This article explains the test models, sample types, procedures, acceptance criteria, and typical applications of ESD protection evaluation.
Technical Overview
Electrostatic discharge (ESD) is the rapid, uncontrolled transfer of electrostatic charge between two objects at different electrical potentials, most commonly between a charged human body, charged production equipment, or a charged device itself and a grounded conductor. Although an ESD event may last only nanoseconds, peak currents can reach several amperes, producing intense local heating and very high electric fields inside a semiconductor device. The consequences range from catastrophic damage, such as gate oxide rupture, junction melt-through, and metal interconnect fusing, to latent defects that pass outgoing inspection yet fail prematurely in the field.
Device ESD protection capability evaluation is the systematic process of applying calibrated, standardized ESD stress waveforms to electronic components in order to measure their withstand voltage, assign a sensitivity classification, and verify compliance with customer specifications and industry qualification requirements. Component-level testing is built on three principal discharge models: the Human Body Model (HBM), the Machine Model (MM), and the Charged Device Model (CDM). These are complemented by transmission line pulsing (TLP) characterization for protection-cell design and debug, and by system-level immunity testing per IEC 61000-4-2 for finished products. Evaluation is typically performed by accredited third-party laboratories using ESD simulators with verified waveform parameters, in accordance with standards published by organizations such as ESDA, JEDEC, IEC, AEC, and ISO.
A complete ESD evaluation program delivers the following outcomes:
- Quantified ESD withstand voltage for every required pin combination, in both positive and negative polarity
- Sensitivity classification (for example, HBM Class 2 or CDM Class C5) against the relevant standard
- Verification of compliance with qualification requirements such as AEC-Q100, AEC-Q101, and AEC-Q200
- Identification of the weakest pins and failure modes through electrical characterization and failure analysis
- Design feedback data, such as TLP I-V curves, triggering voltage, holding voltage, and failure current, for ESD protection optimization
Testing Samples
Integrated Circuits
Logic, analog, mixed-signal, memory, RF, and power management ICs; microcontrollers, SoCs, FPGAs, and ASICs; interface and physical-layer chips for USB, HDMI, MIPI, Ethernet, and PCIe. All common package formats can be evaluated, including QFP, QFN, BGA, LGA, CSP, WLCSP, and lead-frame packages. Evaluation may be performed on packaged units or, for wafer-level reliability programs, directly on wafers using dedicated ESD test structures.
Discrete Semiconductor Devices
Diodes, Schottky diodes, transient voltage suppression (TVS) diodes, bipolar transistors, MOSFETs, IGBTs, thyristors, JFETs, and linear regulators. Discrete devices intended for automotive use are commonly evaluated against the ESD requirements of AEC-Q101, while TVS components are additionally characterized to confirm their clamping performance under defined surge conditions.
Passive and Electromechanical Components
Multilayer ceramic capacitors, thick- and thin-film resistors, inductors, connectors, switch contacts, relays, and quartz crystal units. Although generally more robust than active devices, these components can still exhibit ESD-induced dielectric breakdown or contact degradation, and they are covered by qualification frameworks such as AEC-Q200.
Optoelectronic, Sensor, and MEMS Devices
LEDs, laser diodes, photodiodes, phototransistors, optocouplers, image sensors, MEMS pressure and inertial sensors, and oscillator modules. These technologies frequently combine sensitive active junctions with exposed mechanical structures, making CDM evaluation particularly important.
Finished Assemblies and Subsystems
Printed circuit board assemblies, interface modules, and end products are evaluated at system level per IEC 61000-4-2 to confirm immunity to direct electrostatic discharge from users and service personnel during real-world operation.
Testing Items
Typical ESD protection evaluation programs include the following test items:
- Human Body Model (HBM) ESD robustness testing per ANSI/ESDA/JEDEC JS-001 (superseding legacy methods such as MIL-STD-883 Method 3015 and JESD22-A114)
- Charged Device Model (CDM) ESD testing per ANSI/ESDA/JEDEC JS-002 (formerly JESD22-C101)
- Machine Model (MM) ESD testing per JEDEC JESD22-A115 or AEC-Q101, where still contractually required
- System-level ESD immunity testing per IEC 61000-4-2 and its national adoptions such as GB/T 17626.2
- Transmission Line Pulsing (TLP) and Very-Fast TLP characterization of ESD protection structures
- Pre-stress and post-stress electrical verification, including leakage, parametric, and functional testing
- Failure analysis of failed samples using emission microscopy, thermal imaging techniques, SEM inspection, and FIB cross-sectioning
- Complementary latch-up susceptibility testing per JEDEC JESD78, which is frequently bundled with ESD qualification
Testing Methods
Human Body Model (HBM)
HBM simulates discharge from a charged human fingertip. A 100 pF capacitor is charged to the test voltage and discharged into the device under test through a 1.5 kOhm series resistor, producing a pulse with a rise time of a few nanoseconds and a decay time of approximately 150 ns. Stress is applied between each pin and its associated supply pins, between each pair of supplies, and pin-to-pin as defined by the standard, typically with three positive and three negative pulses per pin at each voltage level. The stress voltage is stepped upward, commonly in 250 V or 500 V increments, until the failure criterion is reached. Devices are classified from Class 0 (less than 250 V) through Class 3B (8000 V and above), with Class 2 (2000 V) being the most widely specified minimum requirement.
Charged Device Model (CDM)
CDM represents the most common real-world ESD threat in modern automated manufacturing: the device package itself becomes charged and then rapidly discharges when one of its pins contacts a grounded surface. In the test, the package is charged either directly or by field induction, and a designated pin is then discharged through a low-inductance probe, generating a sub-nanosecond pulse with peak currents that can exceed ten amperes. Each pin is typically stressed at both polarities at each voltage level, and classification ranges from C1 (125 V) to C7 (1000 V) and above. Because of its fast rise time and high peak current, CDM frequently exposes weaknesses that HBM testing does not, particularly in small-geometry and fine-pitch devices.
Machine Model (MM)
MM simulates discharge from a charged conductive object such as a handler or fixture. The waveform is generated by a 200 pF capacitor discharged with negligible series resistance, producing an oscillatory current with high peak amplitude. Although MM has been largely superseded by CDM in modern qualification flows and removed from some standards roadmaps, it remains contractually referenced by certain automotive and industrial specifications, and accredited laboratories continue to offer it for legacy compliance.
System-Level ESD Immunity per IEC 61000-4-2
For finished products, immunity is evaluated using the IEC 61000-4-2 waveform, generated by a 150 pF capacitor discharged through a 330 Ohm resistor. Contact discharge is applied to conductive accessible surfaces, and air discharge is applied to insulating surfaces, at user-accessible points identified in a test plan. Severity levels extend from Level 1 (2 kV contact) to Level 4 (8 kV contact and 15 kV air), and performance criteria A through D describe whether the equipment continues to operate as intended during and after the discharge. This test validates the complete protection scheme of the product, including on-board TVS devices, board layout, and enclosure design.
Transmission Line Pulsing (TLP)
TLP applies rectangular current pulses, typically 100 ns in duration, at successively increasing amplitudes while measuring the device voltage and current at each step. The resulting quasi-static I-V characteristic reveals the turn-on voltage, snapback holding voltage, dynamic on-resistance, and failure current of the protection structure. TLP data are essential for setting ESD design targets, correlating to HBM and CDM performance, and optimizing the trade-off between clamping effectiveness and signal integrity on high-speed interfaces.
Test Procedure and Failure Criteria
A standard component-level evaluation follows a defined sequence: incoming visual inspection and sample preparation, initial electrical parametric and functional testing to establish a baseline, ESD stress at the starting voltage level, interim electrical testing after each stress level, step-stressing until the failure criterion or the maximum specified voltage is reached, and final classification and failure analysis. Commonly accepted failure criteria include leakage current drift beyond ten times the datasheet limit, parametric values outside specification limits, loss of functionality, or an intermittent connection. Standard-defined sample sizes are used for each pin combination, and because the stress is cumulative and potentially damaging, all evaluated samples are dedicated test units and are never returned to production stock.
Applications
Automotive Electronics
AEC-Q100 requires integrated circuits to meet defined minimum ESD levels, with HBM Class 2 and increasingly stringent CDM targets for Grade 0 and Grade 1 devices, while AEC-Q101 and AEC-Q200 govern discrete and passive components respectively. In-vehicle network transceivers for LIN, CAN, and CAN FD are additionally verified against system-level ESD requirements, making ESD evaluation a mandatory element of automotive product release.
Consumer and Mobile Devices
Smartphones, tablets, wearables, and computers expose USB, HDMI, audio, and SIM interfaces directly to users, so both component-level robustness and system-level immunity per IEC 61000-4-2 Level 4 are routinely specified. TLP-based co-design ensures that protection components clamp effectively without degrading high-speed signal eye diagrams.
Industrial, Communication, and Computing Equipment
PLCs, sensors, Ethernet switches, servers, and base-station equipment must tolerate ESD events in electrically harsh environments. Component CDM qualification protects devices during automated board assembly, while IEC 61000-4-2 immunity testing, often combined with surge and electrical fast transient testing per IEC 61000-4-5 and IEC 61000-4-4, validates complete system robustness.
Medical and Aerospace Electronics
Medical electrical equipment must satisfy the ESD immunity requirements incorporated in IEC 60601-1-2, and aerospace and defense programs frequently impose legacy ESD requirements derived from MIL-STD-883 or MIL-PRF-38535. Accredited laboratory test reports provide the objective evidence needed for regulatory submission and qualification review.
IC Design and Process Qualification
During development, TLP and Very-Fast TLP characterization guide the design of on-chip protection cells, verify the ESD design window against process capability, and support technology qualification for new semiconductor nodes, advanced packaging, and wafer-level products.
FAQ
What ESD withstand level is generally considered acceptable?
Requirements depend on the application. General-purpose commercial ICs are commonly specified at a minimum of 2000 V HBM and 500 V CDM, while automotive Grade 0 and Grade 1 devices per AEC-Q100 typically require 2000 V HBM or higher along with 750 V or higher CDM. Interfaces touched directly by users usually demand system-level immunity per IEC 61000-4-2 at 8 kV contact and 15 kV air discharge or above.
What are the differences between HBM, MM, and CDM?
HBM uses a 100 pF capacitor and 1.5 kOhm resistor to simulate a charged person, producing a relatively slow pulse of about 150 ns. MM uses a 200 pF capacitor with essentially no series resistance, producing an oscillatory high-current waveform representative of charged equipment. CDM charges the device package itself and discharges it through a single pin, generating a sub-nanosecond pulse with the highest peak current and the fastest rise time, which corresponds to the dominant failure mechanism in modern automated manufacturing.
Is ESD testing destructive?
Yes. ESD stress is cumulative and can cause latent degradation even when the device passes electrical testing at a given level. For this reason, evaluation is always performed on dedicated samples, and stressed devices are never shipped as production goods. Step-stress methodologies deliberately drive samples to failure in order to determine the true withstand level with statistical confidence.
How does component-level ESD testing differ from system-level ESD testing?
Component-level testing (HBM, CDM, MM) evaluates the intrinsic robustness of an unpackaged or packaged device during manufacturing and handling, using waveforms defined by ESDA and JEDEC standards. System-level testing per IEC 61000-4-2 evaluates a finished product's immunity to discharge from a charged person, using a different waveform (150 pF through 330 Ohm) applied at accessible points on the enclosure and connectors. Both are needed, because passing component-level tests does not guarantee system-level immunity.
What information does TLP provide, and why is it useful?
TLP extracts the quasi-static I-V behavior of a protection path, including triggering voltage, holding voltage, dynamic resistance, second breakdown current, and power-to-failure. These parameters allow designers to predict HBM and CDM performance, optimize protection cell sizing, and verify that clamping voltages remain safely within the failure window of the protected circuit, all before committing to expensive silicon fabrication.
How are ESD failures identified and diagnosed?
Failures are first detected through post-stress electrical testing, most commonly as leakage current drift beyond specification or as functional and parametric failures. Physical failure analysis then localizes the damage site using techniques such as emission microscopy, lock-in thermography, focused ion beam cross-sectioning, and scanning electron microscopy, confirming the failure mechanism, for example gate oxide rupture, filament formation, or metal melting, and guiding corrective design action.
Which standards govern ESD evaluation?
Principal component-level standards include ANSI/ESDA/JEDEC JS-001 for HBM, ANSI/ESDA/JEDEC JS-002 for CDM, JEDEC JESD22-A115 for MM, JEDEC JESD78 for latch-up, and AEC-Q100, AEC-Q101, and AEC-Q200 for automotive qualification. System-level immunity is governed by IEC 61000-4-2 and national adoptions such as GB/T 17626.2, with medical equipment requirements covered under IEC 60601-1-2.